ABLE OF CONTENTS
Abstract…………………………………………………………………………………………………….iii Dedication………………………………………………………………………………………………….iv Acknowledgements…………………………………………………………………………………………v Table of Contents………………………………………………………………… ………………………vi
Chapter 1 : Introduction ………………………………………………………………………………………………….. 1
1.1 Introduction to System On Chip ……………………………………………………………………………. 1
1.2 Emergence of Network On Chip (NOC) …………………………………………………………………… 1
1.3 Related Work …………………………………………………………………………………………………….. 2
1.4 Problems of NOC………………………………………………………………………………………………… 3
1.4.1 Topology …………………………………………………………………………………………………….. 3
1.4.2 Buffer Size…………………………………………………………………………………………………… 3
1.4.3 Channel Width …………………………………………………………………………………………….. 3
1.4.4 Routing ………………………………………………………………………………………………………. 4
1.5 Project Contribution …………………………………………………………………………………………… 4
1.6 Report Organization ……………………………………………………………………………………………. 5
Chapter 2 : Network On Chip ……………………………………………………………………………………………. 6
2.1 Introduction ………………………………………………………………………………………………………. 6
2.2 On – Chip System Interconnection Overview ………………………………………………………….. 7
2.2.1 Bus – Based System ……………………………………………………………………………………… 7
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2.2.2 The NOC – Based …………………………………………………………………………………………. 8
2.2.3 NOC Designs Issues ………………………………………………………………………………………. 9
Chapter 3 : OASIS Interconnection Network ………………………………………………………………….. 15
3.1 Introduction …………………………………………………………………………………………………….. 15
3.2 OASIS NoC Architecture …………………………………………………………………………………….. 15
3.2.1 Switching ………………………………………………………………………………………………….. 16
3.2.2 Routing …………………………………………………………………………………………………….. 21
3.2.3 Flow Control ……………………………………………………………………………………………… 24
Chapter 4 : OASIS With Run Time Monitoring System………………………………………………………… 26
4.1 Introduction …………………………………………………………………………………………………….. 26
4.2 Algorithm ………………………………………………………………………………………………………… 27
4.2.1 Routing …………………………………………………………………………………………………….. 27
4.2.2 Switching ………………………………………………………………………………………………….. 32
4.3 Architecture …………………………………………………………………………………………………….. 32
4.3.1 Algorithm Implementation in Hardware…………………………………………………………. 33
Chapter 5 : Hardware and Software Evaluation Results ……………………………………………………… 38
5.1 Hardware Complexity ……………………………………………………………………………………….. 38
5.1.1 Logic ………………………………………………………………………………………………………… 38
5.1.2 Power ………………………………………………………………………………………………………. 39
5.1.3 Speed ……………………………………………………………………………………………………….. 39
5.2 Functional Simulation ……………………………………………………………………………………….. 40
5.2.1 Algorithm Verification …………………………………………………………………………………. 40
5.2.2 Packet Delay ……………………………………………………………………………………………… 41
CHAPTER ONE
1.1 Introduction to System On Chip
Complex applications, using System On Chips (SoCs) can be implemented by integrating more cores since the number of cores increases rapidly. That is, the rapid development of cores technology allows complex circuits to be integrated into a single chip. This also means that the system’s complexity also increases; hence designers tend to keep up with the increased complexity by using larger reusable blocks in their system design. However, with these different processing elements used together to achieve powerful systems, connecting these cores together posses a great challenge. And as the number of these computational units/processing units increases and are integrated into one silicon chip, communication between them becomes a problem. A communication system that will support these cores must be designed. Bus – based communication, where bus access request of nodes or cores are serialized through central arbiters, is a simple solution to the communication problem. However, this simple approach presents numerous challenges like scalability problem, bus capacitance increases dramatically with increase bus length and more additional cores, performance penalties, inefficient power or energy as the number of cores increases.
1.2 Emergence of Network On Chip (NOC)
NoC is a concept of communication in System on Chips (SoCs) [6,]. This concept claims to eliminate the problems of the Bus – based communication highlighted above. Unlike Bus – based communication where communication is done through buses and dedicated point-to-point links, Network On Chip, NoC, a more general scheme is adapted, employing a grid of routing nodes spread out across the chip, connected by communication links. The NoC design paradigm is centred communication rather than computation [4]. Each node (or tile) in the on-chip network is composed of a Processing Element (PE) and a communication unit which is so called
2
a Network Interface (NI) as shown in Fig 1 below. The communication between the pairs of nodes is organized by connecting a network of routers and switching packages among them. The traditional bus-based on-chip communication architectures, the NoC solution provides higher communication scalability, flexibility, predictability, and power efficiency.
Fig 1: Regular structure of NoC
1.3 Related Work
Despite the fact that the concept of NoC is a relatively new field, it has in recent times, receive a lot of attention from research community. This is because of it has great potential to solving the On – Chip communication problems. In [6], [19] different NoC topologies are proposed with regular mesh topology being the simplest to implement with most routing schemes. There have been many routing algorithms which are based on wormhole routing proposed for meshes in the literature [7], [8], [10], [15], [16], all aimed at improving the performance of the routing strategies Network on Chip. These routing algorithms can be generally classified into three categories, depending on the degree of adaptiveness provided by the algorithms. A non-adaptive routing algorithm is deterministic and routes a packet from the source to the destination along a unique, predetermined path. A minimal fully adaptive routing algorithm routes all packets through any shortest paths to the destinations. A partially adaptive routing algorithm allows multiple choices for routing packets via shortest paths; in this case, it does not allow all packets to use any shortest paths.
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