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The use of Static Random Access Memory (SRAM)-based Field Programmable Gate Array (FPGA) in critical applications has been considered a solution in space and avionics domain due to its flexibility in achieving multiple requirements such as re-programmability and good performance. However, SRAM-based FPGAs are susceptible to radiation induced Single Event Upset (SEU) that affects the functionality of the implemented design. This research presents the development of an improved Frame Level Redundancy (FLR) Scrubbing algorithm for SRAM-based FPGA to mitigate against radiation-induced SEU. The improved FLR uses Cyclic Redundancy Check (CRC) as an error detection technique to enable configuration memory scrubbing as a solution to mitigate SEU through upset detection and correction. Fault injection was performed on FPGA configuration memory frames on different number of modules to emulate SEU. The improved FLR algorithm was implemented and system level simulation was carried out using MATLAB R2013a. The performance of the improved FLR algorithm was compared with that of the existing FLR algorithm using error correction time and energy consumption as metrics. The results of this work showed that the improved FLR algorithm produced 31.6% improvement in error correction time and 61.1% improvement in energy consumption over the existing FLR algorithm.




1.1 Background of the Study 1
1.2 Motivation 4
1.3 Significance of Research 4
1.4 Statement of Research Problem 5
1.5 Aim and Objectives 6
1.6 Dissertation Organization 6
2.1 Introduction 7
2.2 Review of Fundamental Concepts 7
2.2.1 Field Programmable Gate Array Architecture 7
2.2.2 Single Event Upset 19
2.2.3 Total Ionization Dose 25
2.2.4 Radiation Environment 28
2.2.5 FPGA Single Event Upset Scrubbing Techniques 30
2.2.6 Triple Modular Redundancy 35
2.2.7 Frame Level Redundancy Scrubbing 37
2.2.8 Cyclic Redundancy Check 40
2.2.9 Single Event Upset Detection and Correction Time 42
2.2.10 Power Consumption 43
2.2.11 Fault Injection 45
2.3 Review of Similar Works 47
3.1 Introduction 61
3.2 Generation of Field Programmable Gate Array Configuration Memory 62
3.3 Configuration Memory Triplication 63
3.4 Methodology for a Fault Injection Campaign 64
3.5 Majority Voting Implementation 67
3.5.1 Frame Level Redundancy Scrubbing Process 68
3.6 Majority Voter 71
3.7 Cyclic Redundancy Check 73
3.7.1 Cyclic Redundancy Check Frame Execution 73
3.8 Improved Frame Level Redundancy Scrubbing Algorithm Implementation 74
3.9 Energy Consumption 76
4.1 Introduction 77
4.2 Fault Injection Result 77
4.3 Results of One Module Fault Injection 82
4.3.1 Error Detection versus Module Size 83
4.3.2 Error Correction versus Module Size 85
4.3.3 Energy Consumption versus Number of Frame 86
4.4 Comparison of Improved FLR and Existing FLR Scrubbing Algorithm 96
5.1 Introduction 101
5.2 Conclusion 101
5.3 Significant Contributions 102
5.4 Limitation 102
5.5 Recommendations for Further Work 102
Figure 2.1: Conceptual Layers of a Field Programmable Gate Array 8
Figure 2.2: Generic Structure of an FPGA 9
Figure 2.3: SRAM-Controlled Programmable Switch 11
Figure 2.4: General Structure of an FPGA Bitstream 13
Figure 2.5: Configuration Memory Floor Plan of Virtex-5 FPGA 14
Figure 2.6: Schematic of a 6T SRAM Cell 18
Figure 2.7: Illustration of Configuration Memory 22
Figure 2.8: Configuration Memory used to specify Logic Routing 22
Figure 2.9: Upset in Routing 23
Figure 2.10: Upset in Logic 23
Figure 2.11: Effects of Neutrons on Semiconductor Device 27
Figure 2.12: Scrubbers Classification 32
Figure 2.13: Scrubbing Mechanism 34
Figure 2.14: Implementation on an FPGA TMR 36
Figure 2.15: Frame Level Redundancy Scrubbing Flow Chart 39
Figure 3.1: Snippet of Configuration Memory Triplication Implementation 64
Figure 3.2: FPGA Configuration Memory Fault Injection 65
Figure 3.3: Bit-level Majority Voting in an FLR Scrubbing Technique 70
Figure 3.4: Flow Chart of a Voting Process 70
Figure 3.5: Snippet of bit-level Voting 72
Figure 3.6: Snippet of Cyclic Redundancy Check Implementation 73
Figure 3.7: Improved Frame Level Redundancy Scrubbing Flow Chart 75
Figure 4.1: Single Event Upset in 1 FPGA Module 79
Figure 4.2: Single Event Upset in 2 FPGA Modules 80
Figure 4.3: Single Event Upset in 3 FPGA Modules 81
Figure 4.4: Error Detection time versus Number of Frames for 1 Module Fault Injection 84
Figure 4.5: Error Correction time versus Number of Frame for 1 Module Fault Injection 85
Figure 4.6: Energy Consumption versus number of frames for 1 Module Fault Injection 87
Figure 4.7: Error Detection Time versus Number of Frames for 2 Module Fault Injection 90
Figure 4.8: Error Correction Time versus Number of Frame for 2 Module Fault Injection 90
Figure 4.9: Energy Consumption versus Number of frames for 2 Module Fault Injection 91
Figure 4.10: Error Detection time versus Number of Frames for 3 Module Fault Injection94
Figure 4.11: Error Correction time versus Number of Frame for 3 Module Fault Injection94
Figure 4.12: Energy Consumption versus Number of Frame for 3 Module Fault Injection 95
Figure 4.13: Comparison of Error Correction time versus Number of in a Module for 1 Module Fault Injection between Improved FLR and FLR 98
Figure 4.14: Comparison of Energy Consumption versus Number of in a Module for 1 Module Fault Injection between Improved FLR and FLR 99




1.1 Background of the Study
Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGAs) are Complementary Metal Oxide Semiconductor (CMOS) devices with special characteristic of re-configurability making them desirable for use in systems with evolving technology (Jorge et al., 2015). The use of FPGAs have been shown to provide high computational density and efficiency for many computing applications by allowing circuits to be customized to any application of interest (Wirthlin, 2015). They are attractive to critical applications due to their high performance, power consumption, and reconfiguration capability (Tonfat et al., 2015), and can be re-configured in the field, design updates can be performed while the device is still operational (Kastensmidt & Rech, 2016). Compared to Application Specific Integrated Circuits (ASICs), whose functions cannot be altered after fabrication, SRAM-based FPGAs have the advantage of being reprogrammed and providing a lower cost per device in small quantities (Li, 2012), therefore, there is great interest in exploiting these benefits in space and other radiation environments (Wirthlin, 2015). Configurable FPGAs are better alternative for application specific processing in space based applications because of their flexibility and in-system re-programmability, also FPGAs are versatile devices that allow a function to be implemented by mapping it into the FPGA’s pre-existing logic resources. The mapping is referred to as its configuration (Berg et al., 2008). In SRAM based FPGAs, the mapped circuit is totally controlled by the configuration memory, which is composed of SRAM cells (Reorda et al., 2005). A modern generation FPGA have tens of thousands to millions
system logic gates, with hundreds of millions of configuration bits, dominating the SRAM cells in the device (Jing et al., 2015). Similar to memory devices, FPGAs have high density of transistors and interconnect wires (Stott et al., 2008).
While SRAM-based FPGAs offer several advantages for critical-based operations, they are sensitive to Single Event Upsets (SEUs) (Graham et al., 2003). When a fault changes the state of an SRAM cell, this is referred as SEU (Tambara et al., 2016). In other words, SRAM-based FPGAs are more prone to soft errors since a radiation strike in the configuration memory has a permanent effect on the functionality of the mapped design (Rao et al., 2014). The SRAM-based FPGAs are especially sensitive to SEUs within the configuration memory of the device. The configuration memory defines the operation of the Configurable Logic Blocks (CLBs), routing resources, Input-Output Blocks (IOBs), and other FPGA resources and upsets in the configuration memory can change the operation of the circuit. To ensure proper operation, SRAM-based FPGA circuit designs must mitigate against any configuration memory SEU which could alter the design. Several techniques have been proposed to make designs reliable in the presence of event upsets. Triple Modular Redundancy (TMR) is a technique used to provide design hardening (Graham et al., 2003).
The configuration memory of SRAM-based FPGAs is arranged into segments called configuration frames, and this represents the largest portion of the memory cells in the device. Some factors that increase the susceptibility to soft errors are the reduction of the transistor size and the lower voltage operations of these SRAM memory cells (Tonfat et al., 2015). Therefore, due to small device geometry, a single particle strike might affect multiple adjacent cells in a memory array resulting in a Multiple Bit Upset (MBU). In
addition, increasing transistor count per chip (Moore’s law), aggressive transistor downscaling, and reduced operating voltage result in an exponential growth in soft error of digital circuits in the past years, considering the proliferation use of FPGA devices in various safety and mission-critical applications (Rao et al., 2014). Technology scaling leads to an increase in memory density as well as the probability of SEUs and MBUs in adjacent bits due to particle strike. Soft errors (reversible errors) can be generally tolerated in consumer electronics, but can have adverse effects in mission-critical applications (Eftaxiopoulos et al., 2016). Soft errors in the configuration memory bits of SRAM based FPGAs have a persistent effect and they remain until the original configuration is rewritten (Jorge et al., 2015).
The presence of high energy protons, heavy ions, and galactic cosmic rays in the space and other radiation environment cause a number of problems for electronics, including FPGAs. This radiation can induce a number of negative effects including upsets in the internal state of the device, and can cause several problems in FPGA-based systems. As mentioned earlier, SEUs can corrupt the configuration memory of the device causing the design configured on the device to operate incorrectly (Wirthlin et al., 2016). In SRAM FPGAs, SEUs can affect the configuration and provoke errors that remain until the device is reconfigured. A commonly used method to remove configuration errors is by periodic refresh of the configuration data. This is known as configuration scrubbing. New technologies provide increasing support for configuration scrubbing (Sanchez et al., 2015). Soft error mitigation is crucial for systems operating in harsh environments with high levels of cosmic radiation. Energetic particles generate charge as they traverse the semiconducting materials which gets deposited inducing voltage transients to the
interconnected nodes. (Eftaxiopoulos et al., 2016). Fault masking techniques such as TMR are used to improve the radiation tolerance of circuits implemented in SRAM-based FPGAs. Still, it is necessary to avoid bit upset accumulation in the configuration memory with a correction mechanism to increase the reliability of the circuit (Tonfat et al., 2015).
1.2 Motivation
The SRAM-based FPGA are becoming popular in space and avionic industry because of their large logic resources, re-programmability and broad applicability. The programmability after deployment makes it possible to introduce design update, correct design mistakes thereby extending the system lifetime. The amount of data collected by space vehicle, onboard data processing capabilities enables much data to be interpreted and compressed onboard the space system before transmitting the result to ground station(s) or other space system thus, reducing data transmission requirement. However, radiation strike from high energetic particles in space environment causes the logic state of the SRAM-based FPGA configuration memory to flip resulting to SEU which modifies the function of the FPGA intended design causing the FPGA or system to produce faulty output which can jeopardize the integrity of a system or mission. Therefore, configuration memory scrubbing and some form of reliability are required as solution to address this issue.
1.3 Significance of Research
SEU is a major issue that occurs in processing and storage devices such as FPGA when used in application critical environment like space. SEU is the flipping of logic bit of the configuration memory of FPGA from one state to the other when struck by radiation. This compromises the data integrity as an upset in the configuration memory changes the functionality of the configured circuitry or design which consequently causes malfunction
of the FPGA and could lead to permanent fault when accumulated. Configuration memory scrubbing provides a solution to this problem by mitigating against SEUs and the time to detect and correct SEU is highly critical which has a way of impacting on the energy consumption. There is need to work on a reliable technique that effectively detect and correct SEU within a short period. Therefore, this research work offers a Frame Level Redundancy (FLR) scrubbing algorithm for SRAM based FPGA that employs CRC as an error detection technique to address this issue. This is the reason why this research is significant to carry out in order to discover the improvement of the technique used.
1.4 Statement of Research Problem
A variety of well-known and proven SEU mitigation techniques has been applied to FPGA-based systems and demonstrated in radiation environments. Whenever SRAM-based FPGAs are used, upsets in the configuration memory become a major dependability threat, and must be removed as soon as possible through a process called scrubbing. However, most of the scrubbing techniques impose an overhead in terms of large area, energy consumption and a longer time to correct error. These are some of the problems that arises as a result of mitigating SEU in SRAM-based FPGAs deployed in radiation environment. Therefore, there is need to introduce a technique to explore the trade-off in terms of area, power consumption error correction time and reliability in order to avoid functional failure of the device. As a result of redundancy introduced, this research developed a modified frame level redundancy algorithm as a scrubbing technique to mitigate SEU in SRAM-based FPGAs configuration memory.
1.5 Aim and Objectives
The aim of this research work is to develop an improved FLR scrubbing algorithm for SRAM based FPGA.
The objectives of the research are as follows:
A. Replicate and implement the FLR scrubbing algorithm of Tonfat et al., (2015) used to mitigate SEU in SRAM-based FPGA devices.
B. Develop an improved FLR scrubbing algorithm using CRC as a detection algorithm for SEU to mitigate its effect in FPGA devices.
C. Compare of the performance results of the improved FLR scrubbing algorithm with that of the existing FLR scrubbing algorithm used by Tonfat et al., (2015) in terms of error correction time and energy consumption.
1.6 Dissertation Organization
The organization of this dissertation report is as follows: Chapter one presents the general background of the study; in Chapter two, review of fundamental concepts pertinent to the research work and detailed review of similar works are presented; in Chapter three, detailed explanation of methods and materials are presented; in Chapter four, results and discussions are presented; in Chapter five, conclusions and recommendations are presented; then finally, all the references quoted in this dissertation report and appendices are provided.



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